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Data Sheet PT7C4302 Real-time Clock Module (3-wire Interface)
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Features
* * Using external 32.768kHz quartz crystal Real-time clock (RTC) counts seconds, minutes hours, date of the month, month, day of the week, and year with leap-year compensation valid up to 2099 * * * * * * * * * * 31-byte, nonvolatile (NV) RAM for data storage 2.0V to 5.5V full operation Uses less than 300nA at 2.0V Simple 3-wire interface Serial I/O for minimum pin count Burst mode for reading/writing successive addresses in clock/RAM TTL-compatible (VCC = 5V) Optional industrial temperature range: -40C to +85C Battery backup Trickle charger on chip for rechargeable energy source backup
Table 1 Basic functions of PT7C4302 Item Function Source: Crystal: 32.768kHz 1 Oscillator Oscillator enable/disable Oscillator fail detect Time display 2 Time 12-hour 24-hour
Description
The PT7C4302 serial real-time clock is a lowpower clock/calendar with a programmable square-wave output and 31 bytes of nonvolatile RAM. Address and data are transferred serially via a 3wire bus. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicator. Table 1 shows the basic functions of PT7C4302. More details are shown in section: overview of functions.
Ordering Information
Part Number PT7C4302P PT7C4302W Package 8-Pin DIP 8-Pin SOIC
Note: Lead free package is available by adding "E" after each part number. For example: PT7C4302PE.
PT7C4302 31x8
3
Communicat ion
Century bit Time count chain enable/disable 2-wire I2C bus 3-wire bus Burst mode Write protection External clock test mode Power-on reset override
4 5 6 7
Control RAM Charger Battery backup
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Data Sheet PT7C4302 Real-time Clock Module (3-wire Interface)
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Function Block
PT7C4302
X1
32.768 kHz
CD
OSC
Counter Chain
Time Counter
(Sec,Min,Hour,Day,Date,Month,Year)
31 x 8 RAM
X2
CG
Address Decoder Power Manager
Address Register I /O Interface (3-wires)
SCLK RST I/O
VCC2 VCC1
Shift Registers
Recommended Layout for Crystal
PT7C4302 PT7C4307
Local Ground plane Layer 2 Guard Ring (connect to gound)
Crystal Specifications
Parameter Nominal Frequency Series Resistance Load Capacitance Symbol fO ESR CL Min Typ 32.768 6 Max 45 Unit kHz k pF
The crystal, traces and crystal input pins should be isolated from RF generating signals.
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Data Sheet PT7C4302 Real-time Clock Module (3-wire Interface)
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Pin Configuration
PT7C4302
1
VCC2 X1 X2 GND
VCC1 SCLK I/O RST
8
2
7
3
6
4
5
DIP-8 SOIC-8
Pin Description
Pin no. 1 2 3 Pin VCC2 X1 X2 Type P I O Description Primary power. When VCC2 is greater than VCC1 + 0.2V, VCC2 will power the PT7C4302. Oscillator Circuit Input. Together with X2, 32.768kHz crystal is connected between them. Oscillator Circuit Output. Together with X1, 32.768kHz crystal is connected between them.
4
GND RST I/O SCLK
P
Ground. Reset. The reset signal must be asserted high during a read or a write. This pin has a 40k internal pull-down resistor. Serial Data Input/Output. I/O is the input/output pin for the 3-wire serial interface. The pin has a 40k internal pull-down resistor. Serial Clock Input. SCLK is used to synchronize data movement on the 3-wire serial interface. The pin has a 40k internal pull-down resistor. Backup power. When VCC2 is less than VCC1, VCC1 will power the PT7C4302. VCC1 provides low-power operation in single supply and battery-operated systems as well as low power battery backup. In systems using the trickle charger, the rechargeable energy source is connected to this pin. UL recognized to ensure against reverse charging current when used in conjunction with a lithium battery.
5 6 7
I I/O I
8
VCC1
P
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Data Sheet PT7C4302 Real-time Clock Module (3-wire Interface)
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Function Description
Overview of Functions
1.
Clock function
CPU can read or write data including the year (last two digits), month, date, day, hour, minute, and second. Any (two-digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2099.
2.
Interface with CPU
Simple 3-wire interface.
3.
Oscillator enable/disable
Oscillator can be enabled or disable by /EOSC bit. But time count chain does not shut down when the bit is logic 1.
4.
Charger function
The function is controlled by trickle charge register. Customer can select the charge current by select the number of diode and resistor value through the register. For example: Assume that a system power supply of 5V is applied to VCC2 and a super cap is connected to VCC1. Also assume that the trickle charger has been enabled with one diode and resistor R1 between VCC2 and VCC1. The maximum current IMAX would, therefore, be calculated as follows: IMAX = (5.0V - diode drop)/R1 _ (5.0V - 0.7V) / 2k _ 2.2mA As the super cap charges, the voltage drop between VCC1 and VCC2 will decrease and, therefore, the charge current will decrease.
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Data Sheet PT7C4302 Real-time Clock Module (3-wire Interface)
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Registers
1. Allocation of registers Function Seconds (00-59) Minutes (00-59) Hours (00-23 / 01-12) Dates (01-31) Months (01-12) Days of the week (01-07) Years (00-99) Control Trickle charger Clock burst*7 RAM*9 RAM burst*8 Register definition Bit 7 /EOSC*2 0 12, /24 0 0 0 Y80 WP*3 TCS*4 Bit 6 S40 M40 0 0 0 0 Y40 0 TCS Bit 5 S20 M20 H20 or P /A D20 0 0 Y20 0 TCS Bit 4 S10 M10 H10 D10 MO10 0 Y10 0 TCS Bit 3 S8 M8 H8 D8 MO8 0 Y8 0 DS*5 Bit 2 S4 M4 H4 D4 MO4 W4 Y4 0 DS Bit 1 S2 M2 H2 D2 MO2 W2 Y2 0 RS*6 Bit 0 S1 M1 H1 D1 MO1 W1 Y1 0 RS -
Addr. (hex) *1 00 01 02 03 04 05 06 07 08 1F 20~3E 3F
Caution points: *1. PT7C4302 uses 5 bits for address. It's address byte consists of 1 + RAM/Clock select bit +5-bit addr. + Read/Write select bit. *2. Oscillator Enable bit. When this bit is set to 1, oscillator is stopped but time count chain is still active. *3. WP: Write Protect bit. WP bit should be cleared before attempting to write to the device. *4. TCS: Trickle Charger Select. *5. DS: Diode Select. *6. RS: Resistor Select. *7. Clock burst register address is used as clock/calendar burst mode operation address for consecutively read/write 0~7H registers. Clock/calendar burst mode operation can continuously read 0H to maximum 7H registers in order; write 0~7H registers in order. Less or larger than 8 bytes in clock burst write mode are ignored. *8. RAM burst register address is used as RAM burst mode operation address for consecutively read/write 20~3EH RAM. Less than 31 bytes in RAM burst read/write mode are valid. *9. PT7C4302 has 31x8 static RAM for customer use. It is volatile RAM. *10. All bits marked with "0" are read-only bits. Their value when read is always "0". All bits marked with "-" are customer using space. PT0225(11/05) 5 Ver: 0
Data Sheet PT7C4302 Real-time Clock Module (3-wire Interface)
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2.
Control and status register
Addr. (hex) 07
Description Control (default)
D7 WP 0
D6 0 0
D5 0 0
D4 0 0
D3 0 0
D2 0 0
D1 0 0
D0 0 0
WP: Write Protect bit. WP Read / Write Data 0 1 Write operation is enabled. Prevent a write operation to any other register. Description Default
3.
Time Counter
Time digit display (in BCD code): * Second digits: Range from 00 to 59 and carried to minute digits when incremented from 59 to 00. * Minute digits: Range from 00 to 59 and carried to hour digits when incremented from 59 to 00. * Hour digits: See description on the /12, 24 bit. Carried to day and day-of-the-week digits when incremented from 11 p.m. to 12 a.m. or 23 to 00. Addr. (hex) 00 01 02 Description Seconds (default) Minutes (default) Hours (default) D7 /EOSC* 1 0 0 12, /24 Undefined D6 D5 D4 D3 D2 D1 D0
S40 S20 S10 S8 S4 S2 S1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined M40 M20 M10 M8 M4 M2 M1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 0 H20 or P,/A H10 H8 H4 H2 H1 Undefined Undefined Undefined Undefined Undefined Undefined
* Note: /EOSC bit must be written into 0 to start the time count.
PT0225(11/05) 6
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Data Sheet PT7C4302 Real-time Clock Module (3-wire Interface)
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a)
12 / 24 bit
This bit is used to select between 12-hour clock operation and 24-hour clock operation. 12, /24 Description Hours register 24-hour clock 00 01 02 03 04 05 06 07 08 09 10 11 12-hour clock 92 ( AM 12) 81 ( AM 01 ) 82 ( AM 02 ) 83 ( AM 03 ) 84 ( AM 04 ) 85 ( AM 05 ) 86 ( AM 06 ) 87 ( AM 07 ) 88 ( AM 08 ) 89 ( AM 09 ) 90 ( AM 10 ) 91 ( AM 11 ) 24-hour clock 12 13 14 15 16 17 18 19 20 21 22 23 12-hour clock B2 ( PM 12 ) A1 ( PM 01 ) A2 ( PM 02 ) A3 ( PM 03 ) A4 ( PM 04 ) A5 ( PM 05 ) A6 ( PM 06 ) A7 ( PM 07 ) A8 ( PM 08 ) A9 ( PM 09 ) B0 ( PM 10 ) B1 ( PM 11 )
0
24-hour time display
1
12-hour time display
Be sure to select between 12-hour and 24-hour clock operation before writing the time data. 4. Days of the week Counter
The day counter is a divide-by-7 counter that counts from 01 to 07 and up 07 before starting again from 01. Values that correspond to the day of week are user defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries result in undefined operation. Addr. (hex) 05 Description Days of the week (default) D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 D1 D0
W4 W2 W1 Undefined Undefined Undefined
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Data Sheet PT7C4302 Real-time Clock Module (3-wire Interface)
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5.
Calendar Counter
The data format is BCD format. * Day digits: Range from 1 to 31 (for January, March, May, July, August, October and December). Range from 1 to 30 (for April, June, September and November). Range from 1 to 29 (for February in leap years). Range from 1 to 28 (for February in ordinary years). Carried to month digits when cycled to 1. * Month digits: Range from 1 to 12 and carried to year digits when cycled to 1. * Year digits: Range from 00 to 99 and 00, 04, 08, ..., 92 and 96 are counted as leap years. Addr. (hex) 03 04 06 Description Dates (default) Months (default) Years (default) D7 0 0 0 0 D6 0 0 0 0 D5 D4 D3 D2 D1 D0
D20 D10 D8 D4 D2 D1 Undefined Undefined Undefined Undefined Undefined Undefined 0 0 M10 M8 M4 M2 M1 Undefined Undefined Undefined Undefined Undefined
Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Note: Any registered imaginary time should be replaced by correct time, otherwise it will cause the clock counter malfunction. 6. Trickle Charger Description Trickle charger (default) D7 TCS 0 D6 TCS 1 D5 TCS 0 D4 TCS 1 D3 DS 1 D2 DS 1 D1 RS 0 D0 RS 0
Addr. 8
a) Trickle Charger Select Control the selection of the trickle charger. TCS Data Read/ Write Other patent 1010 Disable the trickle charger Enable the trickle charger
Description * Default 0101
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Data Sheet PT7C4302 Real-time Clock Module (3-wire Interface)
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b) Diode Select Select whether one diode or two diodes are connected between VCC2 and VCC1. DS Data Description 00 or 11 Read/ Write 01 10 The trickle charger is disabled independently of TCS. One diode is selected. Two diodes are selected. * Default
c) Resistor Select Select whether one diode or two diodes are connected between VCC2 and VCC1. RS Data Description 00 Read/ Write 01 10 11 No resistor. R1 with typ. 2k R2 with typ. 4k R3 with typ. 8k * Default
Communication
1. a) 3-wire Interface Command Byte
Figure 1 Command byte The command byte is shown in Figure 1. Each data transfer is initiated by a command byte. The MSB (Bit 7) must be a logic 1. If it is 0, writes to the PT7C4302 will be disabled. Bit 6 specifies clock/calendar data if logic 0 or RAM data if logic 1. Bits 1 through 5 specify the designated registers to be input or output, and the LSB (bit 0) specifies a write operation (input) if logic 0 or read operation (output) if logic 1. The command byte is always input starting with the LSB (bit 0). b) RST and SCL Signal All data transfers are initiated by driving the RST input high and terminated by driving the RST input low. A clock cycle is a sequence of a falling edge followed by a rising edge. For data inputs, data must be valid during the rising edge of the clock and data bits are output on the falling edge of clock. If the RST input is low all data transfer terminates and the SDA pin goes to a high impedance state. Data transfer is illustrated in Figure 2 and Figure 3. At power-up, RST must be a logic 0 until VCC > 2.0V. Also SCLK must be at a logic 0 when RST is driven to a logic 1 state.
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Data Sheet PT7C4302 Real-time Clock Module (3-wire Interface)
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c)
Single Byte Read
Figure 2 Single byte read Following the eight SCLK cycles that input a read command byte, a data byte is output on the falling edge of the next eight SCLK cycles. Note that the first data bit to be transmitted occurs on the first falling edge after the last bit of the command byte is written. Additional SCLK cycles will transmit the same data bytes by PT7C4302 so long as RST remains high. This operation permits continuous burst mode read capability. Also, the SDA pin is tri-stated upon each rising edge of SCLK. Data is output starting with bit 0. d) Single Byte Write
Figure 3 Signal byte write Following the eight SCLK cycles that input a write command byte, a data byte is input on the rising edge of the next eight SCLK cycles. Additional SCLK cycles are ignored. Data is input starting with bit 0. e) Burst Mode Burst mode is specified for either the clock/calendar or the RAM registers by addressing location 31 decimal (Address bits: A4 A3 A2 A1 A0 = 1 1 1 1 1 showed in Figure 1). As before, bit 6 specifies clock or RAM and bit 0 specifies read or write. There is no data storage capacity at locations 9 through 31 in the Clock/Calendar Registers or location 31 in the RAM registers. Reads or writes in burst mode start with bit 0 of address 0. When writing to the clock registers in the burst mode, the first eight registers must be written in order for the data to be transferred. If the number of transferred bytes is less than eight, the data will be ignored. However, when writing to RAM in burst mode, it is not necessary to write all 31 bytes for the data to transfer. Each byte that is written will be transferred to RAM regardless of whether all 31 bytes are written or not. Additional SCLK cycles are ignored. * Clock/Calendar Burst Mode The clock/calendar command byte specifies burst mode operation. In this mode the first eight clock/calendar registers can be consecutively read or written starting with bit 0 of address 0. If the write protect bit is set high when a write clock/calendar burst mode is specified, no data transfer will occur to any of the eight clock/calendar registers (this includes the control register). The trickle charger is not accessible in burst mode. At the beginning of a clock burst read, the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock may continue to run. This eliminates the need to re-read the registers in case of an update of the main registers during a read.
PT0225(11/05) 10
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Data Sheet PT7C4302 Real-time Clock Module (3-wire Interface)
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* RAM Burst Mode The RAM command byte specifies burst mode operation. In this mode, the 31 RAM registers can be consecutively read or written starting with bit 0 of address 0. Note: PT7C4302 use 94H, 96H as test mode address. Customer should not use the address.
Maximum Ratings
Storage Temperature.......................................................................................................................-65oCto +150oC Ambient Temperature with Power Applied...........................................................................-40oCto +85oC Supply Voltage to Ground Potential (Vcc to GND) ..........................................................-0.3V to +6.5V DC Input (All Other Inputs except Vcc & GND)................................................................-0.3V to +6.5V DC Output Voltage (SDA, /INTA, /INTB pins)..................................................................-0.3V to +6.5V Power Dissipation............................................................................................................................320mW (Depend on package)
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended Operating Conditions
Symbol VCC1,VCC2 VIH VIL TA Description Power voltage. VCC = VCC2, when VCC2 > VCC1 + 0.2; VCC = VCC1, when VCC1 > VCC2. Input high level Input low level Operating temperature Min 2 2 -0.3 -40 Type Max 5.5 V VCC+0.3 0.3 85 C Unit
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Data Sheet PT7C4302 Real-time Clock Module (3-wire Interface)
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DC Electrical Characteristics
Unless otherwise specified, GND =0V, TA = 25 C, Oscillation frequency = 32.768kHz. Sym VCC Item Supply voltage Pin VCC1, VCC2 Note 5 OSC on, Note 2,6 ICC1 Current consumption VCC1 OSC on, Note 1,6 OSC off, Note 4,6,8 OSC on, Note 2,7 ICC2 Current consumption VCC2 OSC on, Note 1,7 OSC off, Note 4,7 VIL1 Low-level input voltage VIH1 High-level input voltage VIL2 Low-level input voltage VIH2 High-level input voltage VOL Low-level output voltage SCL, /RST SCL, /RST X1 X1 I/O I/O /RST, SCLK I/O VCC1: 5V VCC1: 2V VCC1: 5V VCC1: 2V VCC1: 5V VCC1: 2V VCC1: 5V VCC1: 2V IOH = 1.5mA, VCC = 2V IOH = 4.0mA, VCC = 5V IOH = -0.4mA, VCC = 2V IOH = -1.0mA, VCC = 5V Note 3 Note 3 VCC1: 2V VCC1: 5V VCC1: 2V VCC1: 5V VCC1: 2V VCC1: 5V VCC1: 2V VCC1: 5V VCC1: 2V VCC1: 5V VCC1: 2V VCC1: 5V Conditions Min 2.0 2.0 1.4 2.0 1.4 1.6 2.4 Typ 0.5 1 100 100 1.1 0.6 1.3 0.9 1.9 0.9 1.9 0.9 0.08 0.11 1.9 4.9 0.7 2 4 8 Max 5.5 0.4 1.2 0.425 1.28 25.3 81 25 80 0.8 0.4 0.8 0.6 0.4 0.4 500 500 Unit V mA A nA mA A A V V V V V V A A V k
VOH High-level output voltage IIL IOZ VTD R1 R2 R3 Input leakage current Output current when OFF Trickle Charge Diode Voltage Drop Trickle charge resistors
Note: 1. I/O open, /RST set to a logic 0, and /EOSC bit = 0 (oscillator enabled). 2. I/O pin open, /RST high, SCLK=2MHz at VCC = 5V; SCLK = 500kHz, VCC = 2.0V, and /EOSC bit = 0 (oscillator enabled). 3. /RST, SCLK, and I/O all have 40k pull-down resistors to ground. 4. /RST, I/O, and SCLK open. The /EOSC bit = 1 (oscillator disabled). 5. VCC = VCC2, when VCC2 > VCC1 + 0.2V; VCC = VCC1, when VCC1 > VCC2. 6. VCC2 = 0V. 7. VCC1 = 0V. 8. Typical values are at 25C.
PT0225(11/05) 12
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Data Sheet PT7C4302 Real-time Clock Module (3-wire Interface)
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AC Electrical Characteristics
Figure 6 a Timing diagram: Read data transfer TA = -40 C to +85 C. Unless otherwise specified. Parameter Data to CLK Setup CLK to Data Hold CLK to Data Delay CLK Low Time CLK High Time CLK Frequency CLK Rise and Fall RST to CLK Setup CLK to RST Hold RST Inactive Time RST to I/O High-Z SCLK to I/O High-Z tDC tCDH tCDD tCL tCH tCLK tR ,tF tCC tCCH tCWH tCDZ tCCZ Sym VCC=2.0V VCC=5V VCC=2.0V VCC=5V VCC=2.0V VCC=5V VCC=2.0V VCC=5V VCC=2.0V VCC=5V VCC=2.0V VCC=5V VCC=2.0V VCC=5V VCC=2.0V VCC=5V VCC=2.0V VCC=5V VCC=2.0V VCC=5V VCC=2.0V VCC=5V VCC=2.0V VCC=5V Min 200 50 280 70
Figure 6 b Timing diagram: Write data transfer
Typ
Max
Unit ns ns
Notes 1 1 1,2,3 1 1 1 1 1 1 1 1 1
800 200 1000 250 1000 250 0 0.5 2.0 2000 500
ns ns ns kHz ns s ns s
4 1 240 60 4 1 280 70 280 70
ns ns
Note: 1. Measured at VIH = 2.0V or VIL = 0.8V and 10ns maximum rise and fall time. 2. Measured at VOH = 2.4V or VOL = 0.4V. 3. Load capacitance = 50pF.
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Data Sheet PT7C4302 Real-time Clock Module (3-wire Interface)
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Mechanical Information
P/PE (8-Pin DIP) 8 .240 .280 1 .355 .400 9.01 10.16 .210 Max 5.33 6.09 7.11 7.62 8.25 .300 .325
.008 .014 0.20 0.35
0 15 .430 Max 10.92
SEATING PLANE X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS
.115 .150 2.921 3.81
.015 Min 0.381 .100 typical 2.54 .014 0.6356 .022 0.558
Note: 1) Controlling dimensions in inches. 2) Ref: JDDEC MS-001 BA
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Data Sheet PT7C4302 Real-time Clock Module (3-wire Interface)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
W/WE (8-Pin SOIC) 8
.149 3.78 .157 3.99
1
.0099 0.25 x 45 .0196 0.50 .0075 .0098 0.40 1.27 .016 .050 0.19 0.25
.189 4.80 .196 5.00
0-8
.016 .026 0.406 0.660 REF
.053 .068
1.35 1.75 SEATING PLANE X.XX X.XX
.2284 .2440 5.80 6.20 DENOTES DIMENSIONS IN MILLIMETERS
.050 BSC
1.27 .013 0.330 .020 0.508
.0040 .0098
0.10 0.25
Note: 1) Controlling dimensions in millimeters. 2) Ref: JDDEC MS-012 AA
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Data Sheet PT7C4302 Real-time Clock Module (3-wire Interface)
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Notes
Pericom Technology Inc.
Email: support@pti.com.cnWeb Site: www.pti.com.cn, www.pti-ic.com China: No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181 Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong Tel: (852)-2243 3660 Fax: (852)- 2243 3667 3545 North First Street, San Jose, California 95134, USA Tel: (1)-408-435 0800 Fax: (1)-408-435 1100
Asia Pacific:
U.S.A.:
Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation.
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